Answer and Explanation:
-- Here we define the AND gate that we need for
-- the Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;
architecture func of andGate is
begin
F <= A and B;
end func;
-- Here we define the XOR gate that we need for
-- the Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity xorGate is
port( A, B : in std_logic;
F : out std_logic);
end xorGate;
architecture func of xorGate is
begin
F <= A xor B;
end func;
-- At this point we construct the half adder using
-- the AND and XOR gates
library ieee;
use ieee.std_logic_1164.all;
entity halfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
end halfAdder;
architecture halfAdder of halfAdder is
component andGate is -- import AND Gate
port( A, B : in std_logic;
F : out std_logic);
end component;
component xorGate is -- import XOR Gate
port( A, B : in std_logic;
F : out std_logic);
end component;
begin
G1 : xorGate port map(A, B, sum);
G2 : andGate port map(A, B, Cout);
end halfAdder;
---------------------------------------------------------END
---------------------------------------------------------END
Test Bench:
--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
entity halfAdder_tb is
end halfAdder_tb;
architecture tb of halfAdder_tb is
component halfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
end component;
signal A, B, sum, Cout: std_logic;
begin
mapping: halfAdder port map(A, B, sum, Cout);
process
variable errCnt : integer := 0;
begin
--TEST 1
A <= '0';
B <= '1';
wait for 10 ns;
assert(sum = '1') report "sum error 1" severity error;
assert(Cout = '0') report "Cout error 1" severity error;
if(sum /= '1' or Cout /= '0') then
errCnt := errCnt + 1;
end if;
--TEST 2
A <= '1';
B <= '1';
wait for 10 ns;
assert(sum = '0') report "sum error 2" severity error;
assert(Cout = '1') report "Cout error 2" severity error;
if(sum /= '0' or Cout /= '1') then
errCnt := errCnt + 1;
end if;
--TEST 3
A <= '1';
B <= '0';
wait for 10 ns;
assert(sum = '1') report "sum error 3" severity error;
assert(Cout = '0') report "Cout error 3" severity error;
if(sum /= '1' or Cout /= '0') then
errCnt := errCnt + 1;
end if;
---- SUMMARY ----
if(errCnt = 0) then
assert false report "Success!" severity note;
else
assert false report "Faillure!" severity note;
end if;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of halfAdder_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END
