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lorasvet [3.4K]
3 years ago
6

Many people hang up on telemarketers, but others will listen politely to their pitches even if they are not interested in the pr

oduct. Telemarketers know that anyone who agrees to listen to a pitch is more likely to buy the product, thanks to the ________ phenomenon.
a. risky shiftb. polarizationc. norm-of-reciprocityd. foot-in-the-doore. door-in-the-face
Social Studies
1 answer:
Harlamova29_29 [7]3 years ago
7 0

<u>Answer:</u>

Telemarketers know that anyone who agrees to listen to a pitch is more likely to buy the product, thanks to the foot-in-the-door phenomenon.  

<u>Explanation:</u>

  • 'Foot-in-the-door phenomenon' is the phenomenon of persuading someone to agree upon a big request after them 'agreeing to a small request'.
  • This phenomenon is based on a principle that when a person agrees upon a small request, there is development of bond between the requester and request.
  • This development of bond will help the requester to make request agree upon his request.  
  • In the above case, if a person agrees to listen to the polite pitches of telemarketers, there is agreement on small request and the probability to buy a product will increase because there is development of bond between them.
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Develop a testbench for the Half Adder that verifies the structural model. The testbench will have no ports. Your testbench shou
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Answer and Explanation:

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use ieee.std_logic_1164.all;

entity andGate is        

  port( A, B : in std_logic;

           F : out std_logic);

end andGate;

architecture func of andGate is

begin

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use ieee.std_logic_1164.all;

entity xorGate is

  port( A, B : in std_logic;

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architecture func of xorGate is

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use ieee.std_logic_1164.all;

entity halfAdder is

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   sum, Cout : out std_logic);

end halfAdder;

architecture halfAdder of halfAdder is

component andGate is -- import AND Gate

     port( A, B : in std_logic;

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component xorGate is -- import XOR Gate

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             F : out std_logic);

  end component;

begin

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end halfAdder;

---------------------------------------------------------END

---------------------------------------------------------END

Test Bench:

--import std_logic from the IEEE library

library ieee;

use ieee.std_logic_1164.all;

entity halfAdder_tb is

end halfAdder_tb;

architecture tb of halfAdder_tb is

component halfAdder is

    port( A, B : in std_logic;

      sum, Cout : out std_logic);

  end component;

signal A, B, sum, Cout: std_logic;

begin

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  process

  variable errCnt : integer := 0;

  begin

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  A <= '0';

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    if(sum /= '1' or Cout /= '0') then

        errCnt := errCnt + 1;

    end if;

---- SUMMARY ----

    if(errCnt = 0) then

      assert false report "Success!" severity note;

    else

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end process;

end tb;

-------------------------------------------------------------

configuration cfg_tb of halfAdder_tb is

  for tb

  end for;

end cfg_tb;

----------------------------------------------------------END

----------------------------------------------------------END

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