Alternative 1:A small D-cache with a hit rate of 94% and a hit access time of 1 cycle (assume that no additional cycles on top of the baseline CPI are added to the execution on a cache hit in this case).Alternative 2: A larger D-cache with a hit rate of 98% and the hit access time of 2 cycles (assume that every memory instruction that hits into the cache adds one additional cycle on top of the baseline CPI). a)[10%] Estimate the CPI metric for both of these designs and determine which of these two designsprovides better performance. Explain your answers!CPI = # Cycles / # InsnLet X = # InsnCPI = # Cycles / XAlternative 1:# Cycles = 0.50*X*2 + 0.50*X(0.94*2 + 0.06*150)CPI= 0.50*X*2 + 0.50*X(0.94*2 + 0.06*150) / X1= X(0.50*2 + 0.50(0.94*2 + 0.06*150) ) / X= 0.50*2 + 0.50(0.94*2 + 0.06*150)= 6.44Alternative 2:# Cycles = 0.50*X*2 + 0.50*X(0.98*(2+1) + 0.02*150)CPI= 0.50*X*2 + 0.50*X(0.98*(2+1) + 0.02*150) / X2= X(0.50*2 + 0.50(0.98*(2+1) + 0.02*150)) / X= 0.50*2 + 0.50(0.98*(2+1) + 0.02*150)= 3.97Alternative 2 has a lower CPI, therefore Alternative 2 provides better performance.
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Hi,
Answer => <span>Inode
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