Wrong..............................................
Answer:
A. 4 CPUs and 6 megabyte cache memory
B. 1.3157 x10^-9 nanoseconds
Explanation:
The Intel core i5 7500 is a seventh generation central processing unit with a 4 CPU core and a 6 megabyte cache memory. It executes task at a clock cycle of 5 clock cycle at a speed of 3.8 GHz.
The relationship between frequency and clock cycle is,
Clock cycle = 1 / ( frequent).
So, One clock cycle = 1 / 3.8 GHz
= 0.3 x10^-9
For five clock cycles = 5 x 0.3 x10^-9
= 1.3157 x10^-9 nanoseconds.
122.255.255.255
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Answer:
Design Phase
Explanation:
In design phase developers make prototypes. The prototype is the solution without actual implementation. That prototype is shown to the user for the purpose of getting feedback. So design phase of SDLC involves making improvements based on user feedback.
Evaluation of one’s own worth is termed as self-esteem. Each person will take the defeat and pointed out mistake in different manner. One person may shout if somebody points out mistake and another may handle it with smile. Self-esteem plays the role here.
Self image is an imaginary of picture of how an individual is in their own perspective and how the same person in the view of other person’s perspective. This is one of the important traits of the people.
Self-value: Setting a value of one self, analyzing various situations and facts and stamping the seal as either “good” or “bad” is called self-value.
