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fredd [130]
3 years ago
7

For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache

Computers and Technology
1 answer:
Sladkaya [172]3 years ago
6 0

Answer:

a) 32 words

b) 32 blocks

c)   374 / 10240

Explanation:

A) Cache block size

The offset bits from given data ; = 5 bits

therefore the cache block size = 2^5 = 32 words

B) determine the number of blocks the cache have

index bits = 5 bits

therefore the number of blocks the cache have = 2^5 = 32 blocks are mapped in the cache

C ) Determine the ratio between Total bits required for such a cache implementation over the data storage  bits

 lets assume

size of each word = w

size of each word ( w ) = 32 * 10 = 320

then we have to determine the total bits = 54 + 320 = 374

also total data bits = 32 * w  = 10240

finally ratio of Total bits over data storage bits

= Total bits / total data bits

=  374 / 10240

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Hi pupil here's your answer ::


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● Data can be read and written on the RAM chip at any number of times.

● The operating system, application programs and the user data is stored in Ram only until the computer is powered on.

● Ram is a volatile memory that loses its contents when the computer is switched off.

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________________________

hope this helps. . . .
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