Question

We begin with a computer implemented in a single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 12 ns. After the stages were split, the measured times were IF, 3 ns; ID, 2.5 ns; EX, 2 ns; MEM, 3 ns; and WB, 1.5 ns. Use 0.1 ns for the pipeline register delay (i.e., the additional time to spend for keeping more registers and logic between pipeline stages).
A. What is the clock cycle time of the 5-stage pipelined machine?
B. If there is a stall every 4 instructions, what is the CPI of the new ?machine?
C. What is the speedup of the pipelined machine over the single- cycle machine?
D. If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine?

Answer 1

Answer:

3.1 ns ; 1.25 ; 3.097

Explanation:

Given :

IF, 3 ns;

ID, 2.5 ns;

EX, 2 ns;

MEM, 3 ns;

WB, 1.5 ns.

Use 0.1 ns for the pipelineregisterdelay

maximum time required for MEM = 3 ns

Pipeline register delay = 0.1 ns.

Clock cycled time of the pipelined machine= maximum time required + delay

3ns+0.1 ns = 3.1 ns

2.) for stall after every 4 instruction :

CPI of new machine :

(1 + (1 /4)) = 1 + 0.25 = 1.25

3.)

The speedup of pipelined machine over the single-cycle machine is given by :

Average time per instruction of single cycle ÷ average time per instruction of pipelined

Clock time of original machine = 12ns

Ideal CP1 = 1

CPI of new machine = 1.25

Clock period = 3.1 ns

(12 * 1) / (1.25 * 3.1) = 12 / 3.875

= 3.097

D. Speed up will equal the number of stages in the machine