Question

Memory module consists of 9 chips. The device is designed with redundancy so that it works even if one of its chips is defective. Each chip contains ???? transistors and function properly if all its transistors work. A transistor works with probability p independent of each other transistor.(a) What is the probability P[C] that a chip works? (b) What is the probability P[M] that the memory module works? (c) If p = 0.999, what is the maximum number of transistors per chip n that produces P[M] ≥ 0.9 (a 90% success probability for the memory module)? (d) If the memory module can tolerate two defective chips, what is the maximum number of transistors per chip n that produces P[M] ≥ 0.9?

Answer 1

Answer:

a) $P[C]=p^n$

b) $P[M]=p^{8n}(9-8p^n)$

c) n=62

d) n=138

Step-by-step explanation:

Note: "Each chip contains n transistors"

a) A chip needs all n transistor working to function correctly. If p is the probability that a transistor is working ok, then:

$P[C]=p^n$

b) The memory module works with when even one of the chips is defective. It means it works either if 8 chips or 9 chips are ok. The probability of the chips failing is independent of each other.

We can calculate this as a binomial distribution problem, with n=9 and k≥8:

$P[M]=P[C_9]+P[C_8]\\\\P[M]=\binom{9}{9}P[C]^9(1-P[C])^0+\binom{9}{8}P[C]^8(1-P[C])^1\\\\P[M]=P[C]^9+9P[C]^8(1-P[C])\\\\P[M]=p^{9n}+9p^{8n}(1-p^n)\\\\P[M]=p^{8n}(p^{n}+9(1-p^n))\\\\P[M]=p^{8n}(9-8p^n)$

c)

$P[M]=(0.999)^{8n}(9-8(0.999)^n)=0.9$

This equation was solved graphically and the result is that the maximum number of chips to have a reliability of the memory module equal or bigger than 0.9 is 62 transistors per chip. See picture attached.

d) If the memoty module tolerates 2 defective chips:

$P[M]=P[C_9]+P[C_8]+P[C_7]\\\\P[M]=\binom{9}{9}P[C]^9(1-P[C])^0+\binom{9}{8}P[C]^8(1-P[C])^1+\binom{9}{7}P[C]^7(1-P[C])^2\\\\P[M]=P[C]^9+9P[C]^8(1-P[C])+36P[C]^7(1-P[C])^2\\\\P[M]=p^{9n}+9p^{8n}(1-p^n)+36p^{7n}(1-p^n)^2$

We again calculate numerically and graphically and determine that the maximum number of transistor per chip in this conditions is n=138. See graph attached.