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kenny6666 [7]
4 years ago
13

The main benefit of shielded twisted pair cabling over unshielded twisted pair is that STP is much more durable.

Computers and Technology
1 answer:
Likurg_2 [28]4 years ago
7 0

Answer: True

Explanation:

In shielded twisted pair (STP) we have two wires which are twisted together and they have a shielding layer outside them which helps them to avoid interference from outside noise. STP thus having the advantage with an additional layer of shield covering the two wires together makes them more durable compared to unshielded twisted pair.

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In the Stop-and-Wait flow-control protocol, what best describes the sender’s (S) and receiver’s (R) respective window sizes?
kolbaska11 [484]

Answer:

The answer is "For the stop and wait the value of S and R is equal to 1".

Explanation:

  • As we know that, the SR protocol is also known as the automatic repeat request (ARQ), this process allows the sender to sends a series of frames with window size, without waiting for the particular ACK of the recipient including with Go-Back-N ARQ.  
  • This process is  mainly used in the data link layer, which uses the sliding window method for the reliable provisioning of data frames, that's why for the SR protocol the value of S =R and S> 1.
3 0
3 years ago
"Bullet Lists" can be which of the following?
MariettaO [177]

Answer:

letters and numbered

Explanation:

7 0
4 years ago
Read 2 more answers
here is an email written by Michelle to Pattie what is the main netiquette violation in sentence b ?​
Artyom0805 [142]

Answer:

Using unfamiliar abbreviations and acronyms

Explanation:

because he using RHFD and LTRE

4 0
3 years ago
A common fallacy is to use MIPS (millions of instructions per second) to compare the performance of two different processors, an
yulyashka [42]

The question is incomplete. It can be found in search engines. However, kindly find the complete question below:

Question

Cites as a pitfall the utilization of a subset of the performance equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4 GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3 GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. 1. One usual fallacy is to consider the computer with the largest clock rate as having the largest performance. Check if this is true for P1 and P2. 2. Another fallacy is to consider that the processor executing the largest number of instructions will need a larger CPU time. Considering that processor P1 is executing a sequence of 1.0E9 instructions and that the CPI of processors P1 and P2 do not change, determine the number of instructions that P2 can execute in the same time that P1 needs to execute 1.0E9 instructions. 3. A common fallacy is to use MIPS (millions of instructions per second) to compare the performance of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. 4. Another common performance figure is MFLOPS (millions of floating-point operations per second), defined as MFLOPS = No. FP operations / (execution time x 1E6) but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the programs.

Answer:

(1) We will use the formula:

                                       CPU time = number of instructions x CPI / Clock rate

So, using the 1 Ghz = 10⁹ Hz, we get that

CPU time₁ = 5 x 10⁹ x 0.9 / 4 Gh

                    = 4.5 x 10⁹ / 4 x 10⁹Hz = 1.125 s

and,

CPU time₂ = 1 x  10⁹ x 0.75 / 3 Ghz

                  = 0.75 x 10⁹ / 3 x 10⁹ Hz = 0.25 s

So, P2 is actually a lot faster than P1 since CPU₂ is less than CPU₁

(2)

     Find the CPU time of P1 using (*)

CPU time₁ = 10⁹ x 0.9 / 4 Ghz

                = 0.9 x 10⁹ / 4 x 10⁹ Hz = 0.225 s

So, we need to find the number of instructions₂ such that  CPU time₂ = 0.225 s. This means that using (*) along with clock rate₂ = 3 Ghz and CPI₂ = 0.75

Therefore,   numbers of instruction₂ x 0.75 / 3 Ghz = 0.225 s

Hence, numbers of instructions₂ = 0.225 x 3 x  10⁹ / 0.75  = 9 x 10⁸

So, P1 can process more instructions than P2 in the same period of time.

(3)

We recall  that:

MIPS = Clock rate / CPI X 10⁶

  So, MIPS₁ = 4GHZ / 0.9 X 10⁶ = 4 X 10⁹HZ / 0.9 X 10⁶ = 4444

        MIPS₂ = 3GHZ / 0.75 X 10⁶ = 3 x 10⁹ / 0.75 X 10⁶ = 4000

So, P1 has the bigger MIPS

(4)

  We now recall that:

MFLOPS = FLOPS Instructions / time x 10⁶

              = 0.4 x instructions / time x 10⁶ = 0.4 MIPS

Therefore,

                  MFLOPS₁ = 1777.6

                  MFLOPS₂ = 1600

Again, P1 has the bigger MFLOPS

3 0
3 years ago
Discuss different ways to respond to errors, such as notifying the user onscreen, writing to an error log, notifying the develop
Ronch [10]

Answer:

Notifying the errors is always useful .

Explanation:

The errors should always be notified to the developer. It is useful and is important. When we provide notifications on the screen, it helps the user and it can be used to provide feedback. In regard to developmental work, it has to be important and confidential and we use the help of email to inform or notify errors to the organization. This will help the company from negative criticism and helps the company perform better. We can also write an error log when we face the same error again and again even after notifying the developer organization. This helps to put a reminder to the organization that immediate check has to be dome and eliminate the error from the source.

Some disadvantages are if we do not keep timer implementation, the alert keeps on popping on the screen, which is irritable.

4 0
3 years ago
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