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SSSSS [86.1K]
3 years ago
10

Consider an unpipelined or single-stage processor design like the one discussed in slide 6 of lecture 17. At the start of a cycl

e, a new instruction enters the processor and is processed completely within a single cycle. It takes 2,000 ps to navigate all the circuits in a cycle (including latch overheads). Therefore, for this design to work, the cycle time has to be at least 2,000 pico seconds. What is the clock speed of this processor? (5 points) What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache? (5 points) What is the throughput of this processor (in billion instructions per second)? (10 points)
Computers and Technology
1 answer:
pantera1 [17]3 years ago
6 0

Answer:

a. Clock Speed of Processor = 0.5 GHz

b. Cycles per Instruction (CPI) = 1 Clock per Instruction

c. Throughput = 1 billion Instruction per Second

Explanation

Given Data

Time Take to complete the single Cycle = 2000ps = 2000 x 10⁻¹²

To Find

a. Clock Speed of Processor = ?

b. Cycles per Instruction (CPI) = ?

c. Throughput = ?

Solution:

a. Clock Speed of Processor = ?

Clock Speed = 1/Time to complete the cycle

                      = 1/2000 x 10⁻¹²  Hz

                      =  0.0005 x 10¹²  Hz

                      =  0.5 x 10⁹  Hz                             as   10⁹ = 1 Giga   so,

                      = 0.5 GHz

b. Cycles per Instruction (CPI) = ?

It is mentioned that, each instruction should start at the start of the new cycle and completely processed at the end of that cycle so, we can say that Cycles per Instruction (CPI) = 1

for above mentioned processor.

c. Throughput = ?

Throughput = CPI x Clock Speed

where

CPI = 1 cycle per instruction

Clock Speed = 1 billion Instructions per Second

as

Clock Speed = 1 billion Cycles per Second

Throughput = 1 cycle per instruction x 1 billion Cycles per Second

Throughput = 1 billion Instruction per Second

                         

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NAND is logically complete. Use only NAND gates to constructgate-level circuits that compute the
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Answer:

Hi, for this exercise we have two laws to bear in mind:

Morgan's laws

NOT(А).NOT(В) = NOT(A) + NOT (B)

NOT(A) + NOT (B) = NOT(А).NOT(В)

And the table of the Nand

INPUT OUTPUT

A B A NAND B

0 0         1

0 1         1

1 0         1

1 1         0

Let's start!

a.

Input            OUTPUT

A       A     A NAND A

1         1             0

0        0            1

b.

Input            OUTPUT

A       B     (A NAND B ) NAND (A NAND B )

0         0            0

0         1            0

1          0             0

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Input            OUTPUT

A       B     (A NAND A ) NAND (B NAND B )

0        0           0

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Explanation:

In the first one, we only need one input in this case A and comparing with the truth table we have the not gate

In the second case, we have to negate the AND an as we know how to build a not, we only have to make a nand in the two inputs (A, B) and the make another nand with that output.

In the third case we have that the OR is A + B and we know in base of the morgan's law that:

A + B = NOT(NOT(А).NOT(В))

So, we have to negate the two inputs and after make nand with the two inputs negated.

I hope it's help you.

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<em />

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<em>    }</em>

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<em>        String FullName = Fname+" "+Lname;</em>

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