Some architectures support the ‘memory indirect’ addressing mode. Below is an example. In this case, the register R2contains a p
ointer to a pointer. Two memory accesses are required to load the data. ADD R3, @(R2)The MIPS CPU doesn’t support this addressing mode. Write a MIPS code that’s equivalent to the instruction above. The pointer-to-pointer is in register $t1. The other data is in register $t4.
