Design a 4-bit register with both shift and parallel load features. The inputs of the register include a 2-bit control code X Y,
a 4-bit input value I3 I2 I1 I0, and a clock signal. The outputs of the register are the 4 bits Q0 Q1 Q2 Q3 corresponding to the value stored in the register. You are allowed to use any number of D flip-flops, muxes of any size, decoders and encoders of any sizes, AND gates, OR gates, and NOR gates. (Notes
1 answer:
Answer:
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Explanation:
The D flip-flop is an edge triggered device which transfers input data to Q on clock rising or falling edge. Data Latches are level sensitive devices such as the data latch and the transparent latch.
See attachment for the step by step solution of the given problem.
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Answer:
See explaination
Explanation:
Here are the steps taken to draw the diagram!
opcode0 and the opcode1 signals are inverted/not to determine the case whether it is 00, 01, 10, 11.
Then they are 'and'ed with the corresponding Zero/lt signal to confirm if the case is true, for eg. zero = 1 if opcode = 00 (beq).
Then all the cases are 'or'ed to get the Branch signal!
See attachment for the diagram
