Terence creates software requirements specification (SRS) documents for various software development projects. In which phase of
the SDLC is Terence involved?
PLS ANSWER SO BRAINLY DOESNT GET RID OF MY ANSWER!
A.
analysis
B.
design
C.
development
D.
testing
E.
implementation
PLS ANSWER SO BRAINLY DOESNT GET RID OF MY ANSWER!
A.
analysis
B.
design
C.
development
D.
testing
E.
implementation
1 answer:
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The question given is incomplete and by finding it on internet i found the complete question as follows:
Direct Mapped Cache.
Memory is byte addressable
Fill in the missing fields based upon the properties of a direct-mapped cache. Click on "Select" to access the list of possible answers Main Memory Size Cache Size Block Size Number of Tag Bits 3 1) 16 KiB 128 KiB 256 B 20 2) 32 GiB 32 KiB 1 KiB 3) 64 MiB 512 KiB 1 KiB Select] 4 KiB 4) 16 GiB 10 Select ] Select ] 5) 10 64 MiB [ Select ] 6) Select] 512 KiB 7
For convenience, the table form of the question is attached in the image below.
Answers of blanks:
1. 3 bits
2. 20 bits
3. 64 MB
4. 16 MB
5. 64 KB
6. 64 MB
Explanation:
Following is the solution for question step-by-step:
<u>Part 1:</u>
No. of Tag bits = No. of bits to represent
Tag bits = Main memory - cache size bits -------- (A)
Given:
Main memory = 128 KB =
Cache Memory = 16 KB =
Putting values in A:
Tag bits = 17 - 14 = 3 bits
<u>Part 2:</u>
Tag bits = Main memory - cache size bits -------- (A)
Given:
Main memory = 32 GB =
Cache Memory = 16 KB =
Putting values in A:
Tag bits = 35 - 15 = 20 bits
<u>Part 3:</u>
Given:
Tag bits = 7
Cache Memory = 512 KB =
So from equation A
7 = Main Memory size - 19
Main Memory = 7 + 19
Main memory = 26
OR
Main Memory =
<u>Part 4:</u>
Given that:
Main Memory Size =
Tag bits = 10
Cache Memory Bits = 34 - 10 = 24
Cache Memory Size =
<u>Part 5:</u>
Given that:
Main Memory Size = 64 MB =
Tag bits = 10
Cache Memory Bits = 26 - 10 = 16
Cache Memory Size =
<u>Part 6:</u>
Cache Memory = 512 KB =
Tag Bits = 7
Main Memory Bits = 19 + 7 = 26
Main Memory size =
i hope it will help you!
