D) All of the above are corect
Answer:
C
Explanation:
I believe that's the answer if it's not sorry
A multilayer switch maybe?? I hope it’s right
Answer:
b. lw $t4, 4($t0)
c. add $t3, $t5, $t4
Explanation:
Pipeline hazard prevents other instruction from execution while one instruction is already in process. There is pipeline bubbles through which there is break in the structural hazard which preclude data. It helps to stop fetching any new instruction during clock cycle.
