Answer:
It might helpful or might be the correct answer to provide the complete question or problem:
This is a testbench design problem, within it, you need to consider the module describing an accumulator.
Explanation:
Consider the following module describing an accumulator:
module accumulator (
output reg: [ 15:0 ] sum, // acumulated out
input [ 7:0 ] in, //in
input rst / clk ) ; //reset and clock inputs
wire carry ;
wire [ 15:0 ] sum_in ;
assign { carry , sum_in } = sum + in ;
alwaysatt ( posedge clock )
if ( rst ) sum ∠ = 0 ; else
sum ∠ = ( carry ) ? 16´hFFFF : sum_in ;
endmodule
From the design code, these are the specifications:
- An active high reset ( rst ) that is synchronous to the positive edge of the clock ( clk ) and clears the output ( sum ) to zero.
- Once reset is removed, the accumulator accumulates summation of the data present on the input ( in ) on every positive clock edge and if the summation exceeds the maximum value that can be represented using a 16-bit number (i.e. 16´hFFFF), the output gets saturated at 16´hFFFF
- The design treats the input data as an unsigned number and produces the output also as unsigned value.
Now write a complete system verilog for this desing that:
(See 1, 2, 3, 4, 5, 6, 7, 8 system requirements)
Defines and uses an interface block to connect to the test program and the DUT.
The interface block should also contain a clocking block and modport statements for defining signal direction to the testbench and to the DUT.
2. Generates the clock signal
3. Applies reset at the beginning
4. Checks the success of the reset operation and displays a success/fail message
5. Makes use of a class for defining random variables and a dynamic array to hold the random values.
6. Constraints the generated random values such that the number of generated random values (i.e. size of dynamic array) is less than 500 and their sum will be greater than 16'hFFFF
7. Applies the generated random values to the design input (in), one at every clock cycle
8. Checks the correctness of the design output (sum) at every clock cycle while applying inputs, and reports if there is a mismatch between the output of the design and the expected output.
Explanation:
