b) Derive the logic expressions for the incrementor and 7-sgement decoder. Since software can perform gate-level optimization, y
ou don’t need to perform simplification. (c) Derive the VHDL code. The basic "skeleton" is library ieee; use ieee.std_logic_1164.all; -- the g, f, ..., a bars of 7-segment LED are mapped to -- hex(6), ..., hex(0) entity inc_7seg_v1 is port ( a: in std_logic_vector(3 downto 0); hex0, hex1: out std_logic_vector(6 downto 0) ); end inc_7seg_v1; -- only and, or, not operators can be used architecture arch of inc_7seg_v1 is signal s: std_logic_vector(3 downto 0); begin -- incrementor (in terms of a(3), a(2), a(1), a(0)) -- S = A + 1; s(3) <= ... ; s(2) <= ... ; ... s(0) <= ... ; -- 1st 7-sgement decoder (in terms of a(3), a(2), a(1), a(0)) hex0(6) <= ... ; ... hex0(0) <= ... ; -- 2nd 7-sgement decoder (in terms of s(3), s(2), s(1), s(0)) hex1(6) <= ... ;
1 answer:
Answer:
Explanation:
Truth Table for Common Cathode 7-segment Hex decoder
PRESENT STATE NEXT STATE COMMON CATHODE
SEVEN SEGMENT
# S3 S2 S1 S0 S3+ S2+ S1+ S0+ g f e d c b a
0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0
2 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1
3 0 0 1 1 0 1 0 0 1 0 0 1 1 1 1
4 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0
5 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1
6 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1
7 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1
8 1 0 0 0 1 0 0 1 1 1 1 1 1 1 1
9 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1
A 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1
B 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0
C 1 1 0 0 1 1 0 1 0 1 1 1 0 0 1
D 1 1 0 1 1 1 1 0 1 0 1 1 1 1 0
E 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1
F 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1
K Maps for Boolean expression is attached
You might be interested in