Answer:
The MSS is 1455
Explanation:
MSS or maximum segment size is the total number of data transferred minus the TCP and IP header. The total number of transmitted frames in a switch network is between 64 bytes to 1518 bytes with a header and trailer. The MSS does not exclude this data-link layer effect but only the transport layer like TCP and UDP, and IP address header, unlike the mtu (maximum transfer unit) which involves all headers.
Answer:
a)
An interrupt is a signal sent to the processor which indicates an event that needs immediate attention.
- Interrupts are usually sent to CPU by external or I/O devices.
-
This notifies the processor to a high-priority process that requires the current process to be disrupted.
- Interrupts requests the processor to stop its ongoing operations and run appropriate part of OS.
- If the request is acknowledged, the processor may respond by halting its current operation, saving its state. Processor then executes a function called an interrupt handler to handle the event that needs attention.
- This interrupt is temporary, and processor continues normal activities after the interrupt operator stops, unless the interrupt shows a fatal error.
- The CPU must inform the device that its interrupt request is acknowledged so that it stops sending interrupt signals.
- Interrupts are usually used for multitasking purposes in real time computers.
- There are two basic types of interrupts: hardware and software interrupts.
- A hardware interrupt requests are generated by hardware devices, to indicate that it needs attention from the operating system.
- Software interrupts are either requested by programs when they want some service from the operating system or these interrupts are generated by processor itself on executing particular instructions or when certain requirements are met.
Approaches to deal with multiple interrupts:
There are two approaches to handle multiple interrupts.
- One approach is to disable interrupts while an interrupt is being processed. A disabled interrupt means that processor will ignore that interrupt request. If during this phase an interrupt happens, it usually remains pending and will be reviewed by the processor after the interrupts has been enabled by the processor. So, when a program is being executed and an interrupt happens, interrupts are disabled immediately.Upon completion of the interrupt handler procedure, interrupts are allowed before the user program resumes, and the processor checks if other interrupts have occurred. This is a simple technique which deals with the interrupts sequentially. But it does not deal with priority requirements.
- Second approach is to define interrupt priorities to enable a higher priority interrupt to cause disruption of a lower-priority interrupt handler. For example take a system with 3 I/O devices: printer, disk and communication line with priorities 3,5, and 7. Lets say when a program starts a printer interrupt happens. The execution continues at printer ISR. At some time interval communication interrupt happens whilst this ISR is still executing. Due to the higher priority of the communication line than the printer, the interrupt is accepted and printer routine is interrupted. Its state is placed on stack and now execution resumes at communication line ISR. Now at some time interval the disk interrupt happens while communication routine is still executing. As the priority of disk interrupt is lower so this is held and communication isr execute completely. Suppose communication ISR finishes, then the previous state is resumed which is printer's ISR execution. But as the disk has higher priority than printer, the processor continues execution in disk ISR. After the completion of disk routine execution, the printer ISR is resumed. After the printer ISR execution is completed the control goes back to the user program.
b) Benefits of using multiple bus architecture compared to single bus architecture are as follows:
- In a multiple bus architecture each pathway is tailored to deal with a specific type of information. This enhances performance as compared to single bus architecture which is used by simple computers to transfer data onto single bus. Performance enhancement is an important reason for having multiple buses for a computer system.
- Multiple bus architecture allows multiple devices to work at the same time. This reduces waiting time and enhances the speed of the computer as compared to single bus architecture in which all the components share a common bus. Sharing a common bus causes bus contention which results in slowing down the computer and waiting time increases.
- Having several different buses available allows to have multiple choices for connecting devices to computer system.
- Bus designs changes, with the introduction of new types and forms from time to time. Multiple bus architecture with several buses can support equipment from different time periods and helps to retain obsolete equipment such as printers and old hard drives, and also add new ones. This is the compatibility benefit of using multiple bus architecture.
- CPU places heavy load on bus which carries data from memory and peripheral traffic. So nowadays computers take on multi core model with multiple buses required. So multiple bus architecture is a good option for such systems as it carries more amounts of data through the processor with minimum wait time.
