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3 years ago

Pls help me with this questions

Mathematics

1 answer:

bazaltina [42]3 years ago

6 0

Step-by-step explanation:

Sn = n/2 [2a + (n-1) d]

(2Sn)/ n = 2a + (n - 1) d

2a + (n-1) d = (2Sn)/n

(n-1) d = (2Sn - 2a)/n

$d = \frac{2sn \: - 2a}{(n(n - 1))}$

$d = \frac{2(sn - a)}{ {n}^{2} - n}$

$d = \frac{2(56 - 25)}{ {32}^{2} - 32}$

d = ¹/16

7a.

E = (mv²)/2 + mgh

E = m( v²/2 + gh)

E/m = v²/2 + gh

E/m - gh = v²/2

2(E/m - gh) = v²

$v = \sqrt{2( \frac{e}{m} - gh)}$

7b.

$v = \sqrt{2( \frac{4900}{20} - 9.8 \times 15)}$

v = 14 m/s

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Memory module consists of 9 chips. The device is designed with redundancy so that it works even if one of its chips is defective

soldier1979 [14.2K]

Answer:

a) $P[C]=p^n$

b) $P[M]=p^{8n}(9-8p^n)$

c) n=62

d) n=138

Step-by-step explanation:

Note: "Each chip contains n transistors"

a) A chip needs all n transistor working to function correctly. If p is the probability that a transistor is working ok, then:

$P[C]=p^n$

b) The memory module works with when even one of the chips is defective. It means it works either if 8 chips or 9 chips are ok. The probability of the chips failing is independent of each other.

We can calculate this as a binomial distribution problem, with n=9 and k≥8:

$P[M]=P[C_9]+P[C_8]\\\\P[M]=\binom{9}{9}P[C]^9(1-P[C])^0+\binom{9}{8}P[C]^8(1-P[C])^1\\\\P[M]=P[C]^9+9P[C]^8(1-P[C])\\\\P[M]=p^{9n}+9p^{8n}(1-p^n)\\\\P[M]=p^{8n}(p^{n}+9(1-p^n))\\\\P[M]=p^{8n}(9-8p^n)$

$P[M]=(0.999)^{8n}(9-8(0.999)^n)=0.9$

This equation was solved graphically and the result is that the maximum number of chips to have a reliability of the memory module equal or bigger than 0.9 is 62 transistors per chip. See picture attached.

d) If the memoty module tolerates 2 defective chips:

$P[M]=P[C_9]+P[C_8]+P[C_7]\\\\P[M]=\binom{9}{9}P[C]^9(1-P[C])^0+\binom{9}{8}P[C]^8(1-P[C])^1+\binom{9}{7}P[C]^7(1-P[C])^2\\\\P[M]=P[C]^9+9P[C]^8(1-P[C])+36P[C]^7(1-P[C])^2\\\\P[M]=p^{9n}+9p^{8n}(1-p^n)+36p^{7n}(1-p^n)^2$

We again calculate numerically and graphically and determine that the maximum number of transistor per chip in this conditions is n=138. See graph attached.