Answer:
Pipelined architecture is 1.667 times more speedy than non pipelined architecture.
Explanation:
There are five stages to to complete an instruction to execute in pipeline architecture. as
Stage 1: Instruction Fetch
Stage 2: Instruction Decode
Stage 3: Execute
Stage 4: Memory Access
Stage 5 : Write Back
The pipeline architecture processed instruction as given below. Each Stage take 1 clock cycle, which is represented as CC.
Stage 1 Stage 2 Stage 3 Stage 4 Stage 5
I1: 1cc 2cc 3cc 4cc 5cc
I2 2cc 3cc 4cc 5cc 6cc
I3 3cc 4cc 5cc 6cc 7cc
I4 4cc 5cc 6cc 7cc 8cc
each four Instructions set takes 8 Clock Cycles.
I5 9cc 10cc 11cc 12cc 13cc
I6 10cc 11cc 12cc 13cc 14cc
I7 11cc 12cc 13cc 14cc 15cc
I8 12cc 13cc 14cc 15cc 16cc
.
.
.
I97: 193cc 194cc 195cc 196cc 197cc
I98 194cc 195cc 196cc 197cc 198cc
I99 195cc 196cc 197cc 198cc 199cc
I100 196cc 197cc 198cc 199cc 200cc
<u>Pipelined architecture Time Calculation</u>
So in pipeline architecture 100 instructions takes 200 clock cycles to execute.
1 Clock Cycle time period is = 60ns.
200 Clock Cycle = 60ns * 200 = 12000 ns
<u>Non Pipelined architecture Time Calculation</u>
1 task Time period= 300ns
100 task time period = 100 * 300 = 30000 ns
The difference between pipelined and non pipelined architecture time period is = 30000 - 12000 = 18000 ns
<u>Speedup ratio</u>
<em>Speed up ratio= 30000/18000 = 1.667</em>
