Answer:
Hi, for this exercise we have two laws to bear in mind:
Morgan's laws
NOT(А).NOT(В) = NOT(A) + NOT (B)
NOT(A) + NOT (B) = NOT(А).NOT(В)
And the table of the Nand
INPUT OUTPUT
A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0
Let's start!
a.
Input OUTPUT
A A A NAND A
1 1 0
0 0 1
b.
Input OUTPUT
A B (A NAND B ) NAND (A NAND B )
0 0 0
0 1 0
1 0 0
1 1 1
C.
Input OUTPUT
A B (A NAND A ) NAND (B NAND B )
0 0 0
0 1 1
1 0 1
1 1 1
Explanation:
In the first one, we only need one input in this case A and comparing with the truth table we have the not gate
In the second case, we have to negate the AND an as we know how to build a not, we only have to make a nand in the two inputs (A, B) and the make another nand with that output.
In the third case we have that the OR is A + B and we know in base of the morgan's law that:
A + B = NOT(NOT(А).NOT(В))
So, we have to negate the two inputs and after make nand with the two inputs negated.
I hope it's help you.
WikiWikiWeb was the first made by <span>Cunningham.</span>
Answer:
// This program is written in C++
// Comments are used for explanatory purpose
// Program starts here
#include<iostream.h>
#include<stdlib.h>
int main()
{
// Declare variables
int num, selectno;
string status;
randomize();
//Generate random number;
num=rand()%10000;
// Prompt to guess a number
cout<<"You have only 10 tries\nTake a guess: ";
int tries = 0;
while (tries != 10)
{
cin>>selectno;
if(selectno == num){
cout<<"You passed at the "<<count+1<<" attempt";
tries = 10;
}
else
{
cout<<"You failed. Take another guess\n You have "<<10 - count + 1 <<" attempts";
}
tries++;
if(tries >= 10)
{
break;
}
}
return 0;
}
Answer: Detailed
Explanation:
SDLC consist of 7 phases. They are:
1. Planning.
2. System analysis and requirement
3. Design:
4. Coding:
5. Testing:
6. Installation
7. Maintenance
Here we are talking of the third phase. In this phase it is the design phase which consist of high and low level design. Here the preliminary design is included in high level design where it describes the required hardware, software, network capabilities and the modelling of the interface. However the detailed design in low level design will implement the coding and will finding of any errors in the implemented design as described by the preliminary design.
