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jek_recluse [69]
2 years ago
13

Which principle suggests that specific single responsibility interfaces are better than one general purpose interface?

Computers and Technology
1 answer:
ElenaW [278]2 years ago
8 0

Answer:Interface segregation principle

Explanation: Interface-segregation principle (ISP) is amongst the major principles of the object-oriented design which describes that none of the users/clients can be forced for indulging and depending on the unknown methods or methods that they don't have knowledge about.

It functions by making the interfaces visible to the user that specifically fascinates them and keeping other smaller interfaces.Interfaces are made by splitting process and making the small interfaces from them.

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What are some industries of aerodynamics and hydrodynamics? explain each one in detail.
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Aerodynamic- Wind turbine, computational fluid dynamics, and Wind power

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(a) How many locations of memory can you address with 12-bit memory address? (b) How many bits are required to address a 2-Mega-
I am Lyosha [343]

Answer:

Follows are the solution to this question:

Explanation:

In point a:

Let,

The address of 1-bit  memory  to add in 2 location:

\to \frac{0}{1}  =2^1  \ (\frac{m}{m}  \ location)

The address of 2-bit  memory to add in 4 location:

\to \frac{\frac{00}{01}}{\frac{10}{11}}  =2^2  \ (\frac{m}{m}  \ location)

similarly,

Complete 'n'-bit memory address' location number is = 2^n.Here, 12-bit memory address, i.e. n = 12, hence the numeral. of the addressable locations of the memory:

= 2^n \\\\ = 2^{12} \\\\ = 4096

In point b:

\to Let \  Mega= 10^6

              =10^3\times 10^3\\\\= 2^{10} \times 2^{10}

So,

\to 2 \ Mega =2 \times 2^{20}

                 = 2^1 \times 2^{20}\\\\= 2^{21}

The memory position for '2^n' could be 'n' m bits'  

It can use 2^{21} bits to address the memory location of 21.  

That is to say, the 2-mega-location memory needs '21' bits.  

Memory Length = 21 bit Address

In point c:

i^{th} element array addresses are given by:

\to address [i] = B+w \times (i-LB)

_{where}, \\\\B = \text {Base  address}\\w= \text{size of the element}\\L B = \text{lower array bound}

\to B=\$ 52\\\to w= 4 byte\\ \to L B= 0\\\to address  = 10

\to address  [10] = \$ 52 + 4 \times (10-0)\\

                       =   \$ 52   + 40 \ bytes\\

1 term is 4 bytes in 'MIPS,' that is:

= \$ 52  + 10 \ words\\\\ = \$ 512

In point d:

\to  base \ address = \$ t 5

When MIPS is 1 word which equals to 32 bit :

In Unicode, its value is = 2 byte

In ASCII code its value is = 1 byte

both sizes are  < 4 byte

Calculating address:

\to address  [5] = \$ t5 + 4 \times (5-0)\\

                     = \$ t5 + 4 \times 5\\ \\ = \$ t5 + 20 \\\\= \$ t5 + 20  \ bytes  \\\\= \$ t5 + 5 \ words  \\\\= \$ t 10  \ words  \\\\

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