Answer:
as pull up network. the metteing point of pull down and pull up is the point where we take the output
note 1: if two n-mos are connected in series it gives logical AND and p-mos paralle gives logical-AND
note 2: if two n-mos are connected in parallel it gives logical OR and p-mos series gives logical-OR
note 3: output is always complement of what we implement
example Y= (AB)'
image attached
A) F = (ABC + D(A+B) )'
pulldown:
this can be realize by takeing three n-mos in series which gives ABC ,two n-mos are parallel which in series with another n-mos whic gives D(A+B), now connect ABC and D(A+B) in parallel
pull up
this can be realize by takeing three p-mos in parallel which gives ABC ,two p-mos are series which is in serires with
another p-mos whic gives D(A+B), now connect ABC and D(A+B) in series
the out put will be (ABC + D(A+B) )'
so we require total 6-mos and 6-pmos total 12mos transistors
B) F = AC + BD
pull down
this can be realize by takeing two n-mos in series which gives AB ,two n-mos are in series
which whic gives BD, now connect AC and BD in parallel
pull up
this can be realize by takeing two p-mos in parallel which gives Ac ,two p-mos are in parallel
which whic gives BD, now connect AC and BD in series
the output is (AC+BD)'
to avoid the complement we have to connect the output to c-mos inverter then we get AC+BD
so we require 5-nmos, 5-pmos total 10 mos transistors
