How does error detection take place

1 answer:

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Answer: To detect and correct errors, additional bits are added to the data bits at the time of transmission. The additional bits are called parity bits. They allow detection or correction of errors. The data bits along with the parity bits form a code word.

Explanation:

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For the SR-latch below high levels of Set and Reset result in Q= 1 and 0, respectively. The next state is unknown when both inpu

dusya [7]

Answer:

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answer : NOR1(q_) wave is complementary to NOR2(q)

Explanation:

Note ; NOR 2 will be addressed as q in the course of this solution while NOR 1 will be addressed as q_

Initial state is unknown i.e q = 0 and q_= 1

from the diagram the waveform reset and set

= from 0ns to 20ns reset=1 and set=0.from the truth table considering this given condition q=0 and q_bar=1 while

from 30ns to 50ns reset=0 and set=1.from the truth table considering this condition q=1 and q_bar=1.so from 35ns also note there is a delay of 5 ns for the NOR gate hence the NOR 2 will be higher ( 1 )

From 50ns to 65ns both set and reset is 0.so NOR2(q)=0.

From 65 to 75 set=1 and reset=0,so our NOR 2(q)=1 checking from the truth table

also from 75 to 90 set=1 and reset=1 , NOR2(q) is undefined "?" and is mentioned up to 95ns.

since q_ is a complement of q, then NOR1(q_) wave is complementary to NOR2(q)