Question

Please refer to the MIPS solution in the question above. How many total instructions are executed during the running of this code? How many memory data references will be made during execution?

Answer 1

Answer:

PLEASE SEE EXPLAINATION

Explanation:

for the code given in C Language :-

for(i=0; i<=100; i++)

{

a[i]=b[i]+C;

}

Given address of a =$a0

Gievn address of b = $a1

$t0 holds i

s0 holds constant C

Assembly Language

addi $t0, $zero, 0

loop: slti $t1, $t0, 101

beq $t1, $zero, exist

sll $t2, $t0, 2

add $t3, $t2, $a1

lw $t3, O($t3)

add $t3, $t3, $s0

add $t4, $t2, $a0

sw $t3, O($t4)

i loop

instructions of 1+101*8=809

101 itereations*2 per itereation sw)=202 data references

Answer 2

Answer:

MIPS designs are used in SGI's computer product line; in many embedded systems; on Windows CE devices; Cisco routers; and video consoles such as the Nintendo 64 or the Sony PlayStation, PlayStation 2 and PlayStation Portable. Most recently, NASA used one of them on the New Horizons probe1.

Explanation:

The earliest MIPS architectures were 32-bit fsfs (generally 32-bit wide data paths and registers), although later versions were implemented in 64-bit. There are five backward compatible revisions of the MIPS instruction set, called MIPS I, MIPS II, MIPS III, MIPS IV, and MIPS 32/64. In the last of these, MIPS 32/64 Release 2, a record control set is defined to major. Also several "extensions" are available, such as the MIPS-3D, consisting of a simple set of floating point SIMD instructions dedicated to common 3D tasks, the MDMX (MaDMaX) made up of a more extensive set of integer SIMD instructions that use 64-bit floating-point registers, MIPS16 which adds compression to the instruction flow to make programs take up less space (presumably in response to the Thumb compression technology of the ARM architecture) or the recent MIPS MT that adds multithreading functionalities similar to the HyperThreading technology of Intel Pentium 4 processors