Question

A. Suppose a CPU with a write-through, write-allocate cache achieves a CPI of 2. What are the read and write bandwidths (measured by bytes per cycle) between RAM and the cache?
b. For a write-back, write allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of 2?

Data Reads per 1000 instructions Data Writes per 1000 instructions Instruction Cahce Miss Rate Data Cache Miss Rate Block size (Bytes)
250 100 0.30% 2% 64

Answer 1

Answer:

Following are the solution to the given question:

Explanation:

In point 1:

I = number of program code completed.  

In such a block of the system memory, the number of iterations to read would be 64/W, while W is the length of its band.

Miss penalty (cycling):

Miss penalty is written for the data cache:

$\to I \times \frac{100}{1000}\times 0.02(\frac{64}{W} + 1)$

Miss penalty for the cache instruction:

$\to I \times 0.003 \times (\frac{64}{W} + 1)$

The $CPI \leq 2$,  Hit time + miss penalty Hit time:

$= I + I \times [0.25 \times 0.02 + 0.1 \times 0.02 + 0.003] \times (\frac{64}{W} + 1) \leq I \times 2.$

$W \geq \frac{64}{99} \` \ 0.646 \frac{Byte}{cycle}.$

In point 2:

Miss penalty read data cache:

$\to I \times 0.25 \times 0.02 \times (1 + 0.3) \times (\frac{64}{W} + 1)$

Miss penalty for the data cache:  

$\to I \times 0.1 \times 0.02 \times(1 + 0.3) \times (\frac{64}{W} + 1)$

Read the penalty for miss:

$\to I \times 0.003 \times (\frac{64}{W} + 1)$

Total runtime = time hit + penalty mismatch

$= I + I \times [0.25 \times 0.02 \times 1.3 + 0.1 \times 0.02\times 1.3 + 0.003]\times (\frac{64}{W} + 1) \leq 2I$

$0.0121 \times (\frac{64}{W} + 1) \leq 1 \\\\ W \geq 0.784 \frac{Byte}[cycle}$