Answer:
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answer : NOR1(q_) wave is complementary to NOR2(q)
Explanation:
Note ; NOR 2 will be addressed as q in the course of this solution while NOR 1 will be addressed as q_
Initial state is unknown i.e q = 0 and q_= 1
from the diagram the waveform reset and set
= from 0ns to 20ns reset=1 and set=0.from the truth table considering this given condition q=0 and q_bar=1 while
from 30ns to 50ns reset=0 and set=1.from the truth table considering this condition q=1 and q_bar=1.so from 35ns also note there is a delay of 5 ns for the NOR gate hence the NOR 2 will be higher ( 1 )
From 50ns to 65ns both set and reset is 0.so NOR2(q)=0.
From 65 to 75 set=1 and reset=0,so our NOR 2(q)=1 checking from the truth table
also from 75 to 90 set=1 and reset=1 , NOR2(q) is undefined "?" and is mentioned up to 95ns.
since q_ is a complement of q, then NOR1(q_) wave is complementary to NOR2(q)
Answer:
D) AND gate.
Explanation:
Given that:
A certain printer requires that all of the following conditions be satisfied before it will send a HIGH to la microprocessor acknowledging that it is ready to print
These conditions are:
1. The printer's electronic circuits must be energized.
2. Paper must be loaded and ready to advance.
3. The printer must be "on line" with the microprocessor.
Now; if these conditions are met the logic gate produces a HIGH output indicating readiness to print.
The objective here is to determine the basic logic gate used in this circuit.
Now;
For NOR gate;
NOR gate gives HIGH only when all the inputs are low. but the question states it that "a HIGH is generated and applied to a 3-input logic gate". This already falsify NOR gate to be the right answer.
For NOT gate.
NOT gate operates with only one input and one output device but here; we are dealing with 3-input logic gate.
Similarly, OR gate gives output as a high if any one of the input signals is high but we need "a HIGH that is generated and applied to a 3-input logic gate".
Finally, AND gate output is HIGH only when all the input signal is HIGH and vice versa, i.e AND gate output is LOW only when all the input signal is LOW. So AND gate satisfies the given criteria that; all the three conditions must be true for the final signal to be HIGH.
Answer:
Decreased risk of structure failure
Answer:
The graph representing the linear inequalities is attached below.
Explanation:
The inequalities given are :
y>x-2 and y<x+1
For tables for values of x and y and get coordinates to plot for both equation.
In the first equation;
y>x-2
y=x-2
y-x = -2
The table will be :
x y
-2 -4
-1 -3
0 -2
1 -1
2 0
The coordinates to plot are : (-2,-4) , (-1,-3), (0,-2), (1,-1) ,(2,0)
Use a dotted line and shade the part right hand side of the line.
Do the same for the second inequality equation and plot then shade the part satisfying the inequality.
The graph attached shows results.
