I think that the answer would be B or C
Answer:
Thank you so much and may god bless you.
Answer:
Timing Diagrams 15 pts. A 10 MHz clock that generates a 0 to 5V pulse train with a 30% duty cycle is connected to input X of a two input OR gate that has a 20nS propagation delay. The clock also goes to an inverter with a 10 ns propagation delay. The output of the inverter goes to the Y input of the OR gate. a) Draw the circuit. 2 pts. b) Plot the output of the clock for two cycles. Show times and voltages. 5 pts. c) On the same page as part (b) plot the output of the inverter. Show times and voltages. 3 pts. d) On the same page as parts (b & c) plot the output of the OR gate. Show times and voltages. 5 pts.
Answer:
a) 
, b) 
Explanation:
The Brinell hardness can be determined by using this expression:
Where 
and 
are the indenter diameter and the indentation diameter, respectively.
a) The Brinell hardness is:
![HB = \frac{2\cdot (1000\,kgf)}{\pi\cdot (10\,mm)^{2}} \cdot \left[\frac{1}{1-\sqrt{1-\frac{(2.50\,mm)^{2}}{(10\,mm)^{2}} } } \right]](https://tex.z-dn.net/?f=HB%20%3D%20%5Cfrac%7B2%5Ccdot%20%281000%5C%2Ckgf%29%7D%7B%5Cpi%5Ccdot%20%2810%5C%2Cmm%29%5E%7B2%7D%7D%20%5Ccdot%20%5Cleft%5B%5Cfrac%7B1%7D%7B1-%5Csqrt%7B1-%5Cfrac%7B%282.50%5C%2Cmm%29%5E%7B2%7D%7D%7B%2810%5C%2Cmm%29%5E%7B2%7D%7D%20%7D%20%7D%20%20%5Cright%5D)
b) The diameter of the indentation is obtained by clearing the corresponding variable in the Brinell formula:
![d = (10\,mm)\cdot\sqrt{1-\left[1-\frac{2\cdot (500\,kgf)}{\pi\cdot (300)\cdot (10\,mm)^{2}} \right]^{2}}](https://tex.z-dn.net/?f=d%20%3D%20%2810%5C%2Cmm%29%5Ccdot%5Csqrt%7B1-%5Cleft%5B1-%5Cfrac%7B2%5Ccdot%20%28500%5C%2Ckgf%29%7D%7B%5Cpi%5Ccdot%20%28300%29%5Ccdot%20%2810%5C%2Cmm%29%5E%7B2%7D%7D%20%20%5Cright%5D%5E%7B2%7D%7D)
The road is in poor condition, slow down.
