Question

When buttons or switches are pressed by humans for arbitrary periods of time, we need to convert a signal level to a pulse. In the following FSM, whenever the input L goes from low to high, the level-to-pulse converter produces a single pulse P, which is one clock period wide. Thus it is a synchronous rising-edge detector. Write a Verilog HDL for the following FSM. L=0 L- Level to pulse 00 Low input, Waiting for risg P0 01 Edge Detected! P=1 / 11 High input, Waiting for fall P=0 LEO CLK converter 1:0NoteDiagram cannot be explained

Answer 1

Answer:

The FSM uses the states along with the generation at the P output on each of the positive edges of the CLK. The memory stores the previous state in the machine and the decoder generates a P output based on the previous state.

Explanation:

The code is in the image.