Question

In this lab, we assumed that the flip-flops did not contribute to the timing constraints of the circuit. Unfortunately, this is not the case. As you saw when you simulated the D flip-flop, the sampling action does not happen instantaneously. In fact, a flip-flop will become unstable if the inputs do not remain stable for a certain amount of time prior to the rising-edge event (setup time) and a certain amount of time after the rising-edge event (hold time). Assume a setup and hold time of 2ns and 1ns, respectively. What would the theoretical maximum clock rate for the synchronous adder be in this scenario

Answer 1

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