Answer:
a. 7.75
b. 24.4
Explanation:
The Operating system uses virtual memory and page tables maps these virtual address to physical address. TLB works as a cache for such mapping.
program >>> TLB >>> cache >>> Ram
A program search for a page in TLB, if it doesn't find that page it's a TLB miss and then further looks for the page in cache.
If the page is not in cache then it's a cache miss and further looks for the page in RAM.
If the page is not in RAM, then it's a page fault and program look for the data in secondary storage.
So, typical flow would be
Page Requested >> TLB miss >> cache miss >>main memory>> page fault >> looks in secondary memory.
Here,
Main memory access time= 30 ns
Page fault rate=.01%
page fault service time= 12ns
TLB access time=7 ns
TLB hit rate= .95%
TLB miss rate =1-.95=.05%
cache access time = 15 ns
cache miss rate= .3%
cache hit rate = 1-.3=.97%
So,
a) TLB hit time= TLB access time = 7 ns
cache hit time = TLB hit rate * TLB access time + TLB miss rate * ( TLB access time + cache hit time)
= .95 * 7 + .05 * (7+15)
= 7.75 ns
b) EAT for TLB hit= 7ns
Total EAT = TLB hit rate *( TLB access time + Cache hit rate * cache access time + cache miss rate * (cache + main memory access time))+ TLB miss rate ( TLB access time + main memory access time + cache hit rate * cache access time + cache miss rate ( cache + main memory access time))
= .95 *( 7 + (.97*15) + .03(15+30))+ .05*(7+30+(.97*15) + .03 ( 15 + 30))=24.4 ns
